1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to controlling the profile of semiconductor features in semiconductor devices.
2. Description of the Related Art
As semiconductor device sizes are scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. As device sizes shrink, increasingly complex etch processes are used to define semiconductor devices features, such as polysilicon gates. For example, a typical gate patterning process may use several steps after the photoresist (“PR”) is patterned, including a hard mask etch step (which uses the PR as a mask), an ARC etch step (which uses the hard mask as a mask), a preliminary cleaning step (which includes some etching action), a break through etch step (to remove oxide), a main poly etch step (which can leave some poly on dielectric outside gate), a soft landing etch step, an overetch step (to clean all polysilicon) and a sidewall clean etch step (which etches sidewalls and potentially gouges the silicon substrate). TEOS (tetra-ethoxy-silane) or silicon nitride may be used as a hard mask. Silicon nitride or amorphous carbon may be used as the ARC layer. Each type of processing may contribute separately to the etching of the polysilicon gate, making it difficult to control the vertical profiles of polysilicon gates. These etch and clean steps—in conjunction with doping, nitrogen implant (for PMOS gates) and implant damage—result in an irregular gate profile that, in many cases, deviates substantially from the ideal vertical sidewall line. For example, the gate can have an “hourglass” shape, a “coke-bottle” shape, or can display a “foot” or notches (aka “mouse bites”) at the bottom and in some cases at the top of the gate. This is shown in FIG. 1 which illustrates examples of various device feature profiles 2-6 formed over a first layer 8 and substrate 7, including an idealized gate profile 2, an hourglass gate profile 3, a gate profile 4 having notches on the top, a gate profile 5 having foot extensions on the bottom, and a gate profile 6 having notches on the bottom.
Smaller device geometries also change the design considerations used in manufacturing semiconductor devices. For example, conventional transistor fabrication processes (such as described in Ghani et al., “100 nm Gate Length High Performance/Low Power CMOS Transistor Structure,” IEDM, p. 415 (1999)) will deliberately create a notch at the base of a gate electrode for purposes of reducing total capacitance, minimizing gate length and lowering parasitic resistance. The use of notches in the gates has a number of drawbacks, including increasing material costs and reducing chip packing density as compared to a gate electrode of the same size having a vertical sidewall profile.
Accordingly, a need exists for a semiconductor manufacturing process which provides better control of the gate sidewall profile. In addition, there is a need for a fabrication process which forms a gate without including notches or mouse bites in the gate sidewall. There is also a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.